The present disclosure generally relates to a memory architecture, and more particularly relates to a memory system providing signal buffering scheme for array and periphery signals.
Memory structures have become integral part of digital processing systems. Generally, it is desirable to incorporate as many memory cells as possible into a given area of memory structure. However, memory cell density is typically constrained by other factors such as layout efficiency, performance, power requirements and noise sensitivity.
The above-mentioned constraints impose limitations upon memory structure designs making it challenging to achieve compact, high performance, and high-bandwidth integrated computing systems. Yield enhancement circuitry for memory integrated circuits is utilized in the art. Memory integrated circuits are formed of multiple arrays of memory cells. Each memory array is constructed of rows and columns of memory cells. Normally, the rows of memory cells are selected by an address decoder. The columns of memory cells are bounded by read/write buffers that retrieve data from and store data to the selected memory cell. A column decoder provides a selection mechanism to guide data from a selected column to the read/write buffers. The output of the read/write buffer is transferred to an input/output driver and receiver to transfer the data between the memory cells and external circuitry.
FIG. 1 is a schematic diagram illustrating a global and local inversion scheme for array and periphery signals as re-buffered, according to the related art. According to the related art scheme, a global signal and a local signal for bit cell array are opposite in polarity. As these signals are running along long lines, the opposite polarity aggravates the coupling issue, which deteriorates a slope of a local signal LOCAL SIGNAL_A heavily at the 90% to 100% region. Also, the periphery signal is re-buffered and has a single metal line which leads to relatively higher resistor-capacitor (RC) delay with respect to the array signal, thereby deteriorating the performance of design. Further, the array signal and the periphery signal should be able to track each other to have similar read and write performance at different columns.
Therefore, there is a need for a memory architecture based on varying columns in order to optimize performance and area utilization. Additionally, the architecture is adapted to provide signal buffering scheme for array and periphery signals.